instruction fetch cycle
prise en charge (d'une instruction)
fetch cycle oor Frans
fetch cycle
Vertalings in die woordeboek Engels - Frans
cycle d'extraction et d'exécution
cycle d'instruction
Geskatte vertalings
Vertoon algoritmies gegenereerde vertalings
Soortgelyke frases
voorbeelde
Advanced filtering
Voorbeelde moet herlaai word.
As a result, during the next instruction fetch cycle, the target instruction is fetched for execution.
Dans l étude en première ligne de traitement dans la LLC, les patients ayant un stade C de Binet dans le groupe R-FC ont présenté plus d effets indésirables que ceux du groupe FC (R-FC # % vs FC # %patents-wipo patents-wipo
During the fetch cycle, multiple instructions are simultaneously fetched from storage in physical memory order and rotated into a PC-related issue order within the rotate and dispatch block.
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The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window.
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During the fetch cycle in which the branch instruction is fetched, the displacement portion (124) of the branch instruction is reinserted into the address register (20) as the address of the next instruction to be fetched.
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She’ll soon be here to fetch her cycling bloomers.
La position du gouvernement consiste-t-elle à dire que nous n'avons été ni surpris ni troublés de cette situation?Literature Literature
Hence, the branch processing latency found in prior systems in which the next fetch cycle is skipped while the branch target address is computed, such as by adding an offset to the program counter (12) value, is eliminated.
Diminution de la forcepatents-wipo patents-wipo
The hyperSPARC has an on-die 8 KB instruction cache, from which two instructions were fetched per cycle and decoded.
tout troupeau de bovins ne répondant pas aux critères visés sous #°, #°, #° et #°, ou un troupeau dont le statut sérologique pour l'I.B.R. est inconnuWikiMatrix WikiMatrix
Previously accessed blocks remain in their corresponding latches until the pre-fetch process 'cycles around' and overwrites the contents of each sequentially-accessed latch.
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In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.
Au vu des considérations qui précèdent, l'Autorité a décidé d'ouvrir la procédure formelle d'examen conformément à l'article #er, paragraphe #, de la partie I du protocole no # de l'accord Surveillance et Courpatents-wipo patents-wipo
A digital sampling instrument having the features of non-redundant data loading, single-cycle-fetch-and-store memory operations, and volume scaling.
Le règlement (CE) no #/# de la Commission établit les modalités d’application des restitutions à l’exportation dans le secteur des fruits et légumespatents-wipo patents-wipo
The way prediction unit is intended for high frequency microprocessors in which associative caches tend to be clock cycle limiting, causing the instruction fetch mechanism to require more than one clock cycle between fetch requests.
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Therefore, an instruction fetch can be made every clock cycle using the predicted fetch address until an incorrect next fetch address or an incorrect way is predicted.
LOI ANTIPAUVRETÉpatents-wipo patents-wipo
The vector load unit may cause the complex data items to be fetched each clock cycle for use by any datapath in the complex arithmetic logic unit execution pipeline.
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They haven’t cycled off to fetch the milk, but they’ve fired the day’s first spliff.
Posséder une expérience approfondie du petit élevageLiterature Literature
To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC.
On n' a rien trouvépatents-wipo patents-wipo
In a system including a control processor (5), a coprocessor (19), a program memory (7) and a data memory (8), the control processor accessing the program memory during an instruction fetch cycle and the data memory during an instruction execution cycle, an apparatus for controlling access to said data memory has a control processor interface for coupling to the control processor, a coprocessor interface for coupling to the coprocessor, and instruction fetch detection logic, coupled to the control processor interface means, for detecting when the control processor requests access to the program memory and generating, in response, a first access signal.
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The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.
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Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
La décision dpatents-wipo patents-wipo
The instruction dispatching method includes, in an instruction execution period having a plurality of execution cycles, successively fetching and issuing an instruction for each of a plurality of instruction execution threads according to an allocation of execution cycles of the instruction execution period among the plurality of instruction execution threads.
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During the next clock cycle, selected ones of the previously fetched and rotated instructions enter the issue cycle, a new set of instructions are fetched in physical memory order, the previously fetched and rotated instructions which were not issued are rearranged into physical memory order and mixed in physical memory order with the newly fetched instructions, together all fetched and non-issued instructions are rotated into issue order prior to the next issue cycle, and so forth until all instructions have passed through the pipeline.
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Remaining execution cycles are subsequently used to successively fetch and issue another instruction for each of the plurality of instruction execution threads having at least one remaining allocated execution cycle of the instruction execution period.
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During each cycle, a group of packets from the stream may be fetched according to QoS parameters.
Nombre de montagespatents-wipo patents-wipo
Therefore, interrupt instructions are fetched and jammed into a pipelined instructions stream (16) regardless of instruction cycle boundaries.
Une association allemande d’importateurs/distributeurs a par ailleurs formulé des commentaires et a été entendue de même que des importateurs/distributeurspatents-wipo patents-wipo
By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory (206) access problem.
Dispositions généralespatents-wipo patents-wipo
After reset, the EA pin (320) operates as a bidirectional control pin that, as an output, signals whether the current bus cycle is an instruction fetch, and, as an input, signals whether the microcontroller (302) shall read the data present on a certain set of I/O pins.
Certaines substances autres que les vitamines et les substances minérales ou les ingrédients qui en contiennent sont ajoutées aux denrées alimentaires sous forme d'extraits ou de concentrés, et peuvent entraîner des apports nettement supérieurs à ceux qui pourraientêtre ingérés dans le cadre d'un régime adéquat et variépatents-wipo patents-wipo
48 sinne gevind in 16 ms. Hulle kom uit baie bronne en word nie nagegaan nie.