Besonderhede van voorbeeld: 4912081022195400636

English

Again, there are many other ways this can be expressed in VHDL. -- latch template 1: Q <= D when Enable = '1' else Q; -- latch template 2: process(D,Enable) begin if Enable = '1' then Q <= D; end if; end process; The D-type flip-flop samples an incoming signal at the rising (or falling) edge of a clock.

Korean

VHDL에서 D 래치는: -- latch template 1: Q <= D when Enable = '1' else Q; -- latch template 2: process(D,Enable) begin if Enable = '1' then Q <= D; end if; end process; D 플립플럽 클럭 신호 상승 또는 하강 엣지에서 입력 D가 출력 Q에 반영된다.