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Author: WikiMatrix
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English[en]
A simple AND gate in VHDL would look something like -- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic); end entity ANDGATE; -- this is the architecture architecture RTL of ANDGATE is begin O <= I1 and I2; end architecture RTL; (Notice that RTL stands for Register transfer level design.)
Basque[eu]
Bi sarrerako ETA ate logiko baten inplementazioa honako itxura izango luke VHDL lengoaian: -- (hau VHDLko iruzkin bat da) -- std_logic inportatu IEEE liburutegitik -- kodea hemen hasten da library IEEE; use IEEE.std_logic_1164.all; -- hau entitatea da entity ANDGATE is port ( IN1 : in std_logic; IN2 : in std_logic; OUT1: out std_logic); end ANDGATE; -- hau arkitektura da architecture RTL of ANDGATE is begin OUT1 <= IN1 and IN2; end RTL; ABEL Verilog