single instruction, multiple data oor Spaans
single instruction, multiple data
Vertalings in die woordeboek Engels - Spaans
datos múltiples de instrucción única
Geskatte vertalings
Vertoon algoritmies gegenereerde vertalings
Single Instruction, Multiple Data
en
A technique employed to achieve data level parallelism, as in a vector processor.
Vertalings in die woordeboek Engels - Spaans
Instrucción Única para Múltiples Datos
en
A technique employed to achieve data level parallelism, as in a vector processor.
es
Técnica empleada para alcanzar paralelismo a nivel de datos, como en un procesador vectorial.
Geskatte vertalings
Vertoon algoritmies gegenereerde vertalings
voorbeelde
Advanced filtering
Voorbeelde moet herlaai word.
Multiple Single Instruction Multiple Data (MSIMD) architectures;
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Multiple Single Instruction Multiple Data (MSIMD) architectures;
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Paralelization was implemented on multi-core multi-threaded architectures, us- ing the Flynn Single Instruction Multiple Data taxonomy.
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Essentially in a SlMD or single instruction multiple data execution model, we actually have multiple processing units.
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Single Instruction Multiple Data (SIMD) architectures such as vector or array processors
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The single-instruction-multiple-data (SIMD) classification is analogous to doing the same operation repeatedly over a large data set.
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Additionally while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like SIMD (Single Instruction Multiple Data) vector processors began to appear.
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So we it one very common extension to the Von Neumann model is single instruction multiple data execution in the, in the design of processing units.
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For simple, cost-reduced RISC-V systems, there is a proposal to use the floating-point registers' bits to perform parallel single instruction, multiple data (SIMD) sub-word arithmetic.
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The present invention relates to a dynamically reconfigurable hybrid Single Instruction, Multiple Data (SIMD) / Multiple Instruction, Multiple Data (MIMD) architecture of a coprocessor used in high-performance systems for computerised vision tasks.
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SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. SSE2 was first introduced by Intel with the initial version of the Pentium 4 in 2001.
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This leads to a SIMD (single-instruction stream, multiple-data stream) architecture.
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Major changes are the omission of the S-cache, a larger I-cache, and the inclusion of Motion Video Instructions (MVI), an extension to the Alpha Architecture which introduced single instruction multiple data (SIMD) instructions for improving the performance of MPEG encoding.
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The clusters are near identical except for two differences: U1 has a seven-cycle pipelined multiplier while U0 has a three-cycle pipeline for executing Motion Video Instructions (MVI), an extension to the Alpha Architecture defining single instruction multiple data (SIMD) instructions for multimedia.
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Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like SIMD (Single Instruction Multiple Data) vector processor s began to appear. These early experimental designs later gave rise to the era of specialized supercomputer s like those made by Cray Inc.
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Multiple-instruction-single-data (MISD) is a rarely used classification.
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Also in case of single instruction stream, multiple data stream—a case when a lot of data from the same type has to be processed—, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monotonous program engines such as video creation software and photo processing.
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Flynn classified programs and computers by whether they were operating using a single set or multiple sets of instructions, and whether or not those instructions were using a single set or multiple sets of data.
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51 sinne gevind in 28 ms. Hulle kom uit baie bronne en word nie nagegaan nie.