A simple AND gate in VHDL would look something like -- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic); end entity ANDGATE; -- this is the architecture architecture RTL of ANDGATE is begin O <= I1 and I2; end architecture RTL; (Notice that RTL stands for Register transfer level design.)
Horrez gero ez dago beste zer ikusirik Yonvillen. Kalea (bakarra), fusil tirabide bateko luzerakoa eta zenbait dendaz hegitua, Bat-batean bukatzen da kamioaren bihurgunean.WikiMatrix WikiMatrix